1. Field of the Invention
Embodiments of the invention relate to the field of semiconductors, and more specifically, to device testing.
2. Description of Related Art
As the complexity of Integrated Circuits (ICs) increases, the costs of testing ICs have also increased. To address the problem, several testing methodologies have been developed including those using Design For Test (DFT) techniques and Automated Test Equipment (ATE). DFT methodology focuses on the design of Built-in Self Test (BIST) with internal circuitry. ATE methodology focuses on developing external test controllers with interface to the DUTs. In general, test using BIST is significantly faster than ATE, but it has limited fault coverage. ATE, on the other hand, achieves higher fault coverage but usually incurs longer test time.
One major problem in testing ICs is the Input/Output (I/O) communication between the external tester (e.g., ATE) and the Device Under Test (DUT). A high number of I/O pins for a DUT adds to the complexity of test interface hardware and procedure. Even for Low Pin Count (LPC) devices, this number may still be high, especially when multiple devices are tested at the same time.